• 面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 工作經歷不拘 18天前更新
    【本職缺接受台積電官方網站與1111投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4290&source=1111&tags=2024DomesticCampus_1111 Description: 1. Quality and Reliability roles. 2. Failure & TEM analysis, Reliability data analysis, manufacturing production quality management and reliability assessment, research, and development of new analysis protocol. 3. Customers problem resolving for production quality / reliability issues. Qualifications: 1. Master‘s degree or above in electrical engineering, materials science, chemistry, physics, mechanical engineering or related science and engineering areas. 2. Statistics or machine learning background for data analysis and statistics development & application related roles.
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  • 月薪38700元 新竹縣寶山鄉 工作經歷不拘 18天前更新
    【本職缺接受台積電官方網站與1111投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4288&source=1111&tags=2024DomesticCampus_1111 Description: Task: 1. 你喜歡動手解決精密機械、設備問題嗎? 2. 你想要突破半導體機台量產技術的極限,並持續挑戰未來科技的無限可能嗎? 3. 〝模組副工程師〝就是最適合你的位置,你將運用最先進的操作系統及AI人工智慧界面來進行設備維修、保養,與公司一起成長,共同突破機台的生產極限,成為推動半導體領域解決問題的工程專業人才! Job Content: 1. 負責半導體產品線機台設備維修及保養 2. 管理及改善機台零件系統、包含廠商與下包商之零件備品管理 3. 設計機台保養制具及流程改善以增進機台穩定性 4. 需配合日、夜/假日班輪值(約每四週輪值一次大夜班,一次輪值六天) 5. 加入TSMC ,訓練成為模組副工程師後, 您將享有: A. 挑戰百萬年薪: (1) 高競爭力的薪資水準及獎酬機制 (2) 夜班獎金:每月輪值大夜班一次(六天)除夜班津貼外,另發放鼓勵獎金NT$8,000,每月輪值均能領取,等於每月加薪NT$8,000 (未滿六天按比率計算 ) (3) 分紅獎勵:每季依公司營運獲利分享業績獎金, 讓您1年、4季、12個月都能領取豐厚的薪資獎酬 B. 豐富寬廣的培訓發展,以及職涯升遷: (1) 專業訓練:全球最先進的中科訓練中心,十二吋廠儲備模組副工程師安排六周全職訓練課程 (2) 職涯升遷:垂直往上或水平轉換的職務機會,永不設限 C. 高規格的工作環境: (1) 美食饗宴:24小時提供多樣化異國美食 (2) 休假優給:給予優於勞基法之彈性休假及病假 Qualifications: 1. 具備大學學歷,且為電機、電子、機械、自動控制、冷凍空調工程等相關科系 2. 需有機械相關的基礎知識;有半導體製程知識者尤佳 3. 需有問題解決、溝通表達、團隊精神、主動學習等能力 4. 需有基本英文讀寫能力 5. 需能配合大多數工作時間內,穿著無塵衣且將在無塵室環境中工作 6. 需經過至多十二個月的相關訓練並通過認證,始得成為模組副工程師 7. 薪資:起薪38,700元起,年薪含分紅獎金、大夜津貼、夜班獎金、額外獎金
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  • 面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 工作經歷不拘 18天前更新
    【本職缺接受台積電官方網站與1111投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4287&source=1111&tags=2024DomesticCampus_1111 Description: TSMC‘s advanced packaging process is an efficient and high-density packaging technology that mainly targets the demand for high-performance semiconductor components, including microprocessors, graphics processors, artificial intelligence chips, etc. This technology uses advanced 3D stacking technology to vertically stack multiple chips and uses high-density packaging materials to fix them together. This technology can improve the performance of components, reduce power consumption, reduce package size, and increase system integration. TSMC‘s packaging process includes various technologies such as CoWoS, InFO. Among them, CoWoS is a technology that connects different chips through copper wires through silicon interconnect technology to achieve high-frequency and high-speed data transmission. InFO technology directly encapsulates chips on the substrate, connecting chips and substrates through tiny copper wires, achieving a more compact and efficient packaging solution. TSMC‘s advanced packaging process can improve chip performance and production efficiency, and meet the packaging technology requirements of modern high-performance electronic products, such as smartphones, artificial intelligence, high-performance computing, and other fields. TSMC‘s advanced packaging organization include Testing R&D Engineer conduct exploratory research in DFT test architecture, evaluate next-gen test technology of several device( logic SOC, HPC, AP, RF, etc.),which used 3D silicon stacking and advanced packaging technologies and closely teamwork with international customer from new product introduction to mass production. Qualifications: 1. Bachelor‘s degree or above in Electrical/Electronic engineering, Computer engineering, Communication, Optical electronics or related fields. 2. Solid technical understanding of semiconductor testing concept. 3. Familiar with programming language. 4. Hands-on participation and a strong sense of ownership. 5. Fluent in English and exhibit good communication skills to work within cross-functional teams.
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  • 面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 工作經歷不拘 18天前更新
    【本職缺接受台積電官方網站與1111投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4294&source=1111&tags=2024DomesticCampus_1111 Description: 【Finance Associate】 The candidate will be positioned and rotate among different functions within Finance Division, including Financial Planning, Investment Management, Foreign Exchange Management, Funding and Cashier, Treasury Investment, Customer Credit, and SEC Compliance. 【Accounting Associate】 1. Provides financial information to management by researching and analyzing accounting data; preparing reports. 2. Rotate within Accounting: Reporting & Analysis Dept., Account service Dept.(Operations, R&D and SG&A), General Accounting Dept., Forecast and Planning Dept. Qualifications: 【Finance Associate】 1. MBA Graduate with excellent English. 2. 3-year experiences in banking or corporate finance will be a plus. 3. Excellent interpersonal, negotiation, and troubleshooting skill. 4. High EQ; capable of dealing with constructive confrontation. 5. Self-motivated and team player. 6. Skilled in MS Word, Excel and PowerPoint. 【Accounting Associate】 1. Bachelor‘s degree or above. 2. Major in Accounting or related field. 3. Working experiences in well-known international Accounting firms will be a plus. 4. CPA license will be a plus. 5. Engineering and computer science majors will be a plus.
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  • 面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 工作經歷不拘 18天前更新
    【本職缺接受台積電官方網站與1111投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4289&source=1111&tags=2024DomesticCampus_1111 Description: 1. Development and integration of Factory Automation Systems, or 2. Development and integration of Advanced Technology, or 3. Development and integration of Office Automation Systems, or 4. Development and integration of Cloud Computing, Kubernates or BigData Analytics Systems, or 5. Build/Development Scalable Platform for managing container applications. Qualifications: 1. Major in IT, Computer Engineering, Software Engineering, Computer Science or related fields. 2. Familiar with development of C/C++ or JAVA Programming, or 3. Familiar with Microservices Architecture Pattern, DevOps or 4. Familiar with Web Applications for PC and Mobiles, or 5. Familiar with Hadoop, Spark and Parallel Computing. 6. The ones with multiple above skill sets and experience is a plus. 7. Experience in large-scale system integration, cloud computing, social networking for factory automation is a plus. 8. Self-motivated, integrity, and result-oriented personality.
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  • 面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 工作經歷不拘 18天前更新
    【本職缺接受台積電官方網站與1111投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4300&source=1111&tags=2024DomesticCampus_1111 Description: 您可以根據所希望的工作地點和職務,投遞您的履歷到我們官網的以下職位: 1. 實驗室技術員 2. 龍潭先進封裝製造部技術員 3. 龍潭先進封裝工程部技術員 4. 竹科製造部技術員(12吋廠) 5. 竹科工程部技術員(12吋廠) 6. 竹科電子束作業處技術員 7. 竹科物流運籌系統部技術員 8. 竹南先進封裝製造部技術員 9. 竹南先進封裝工程部技術員 10. 中科技術員 11. 南科物流運籌系統部技術員 12. 南科製造部技術員(8吋廠) 13. 南科製造部技術員(12吋廠) 14. 南科工程部技術員(12吋廠) 15. 高雄製造部技術員(12吋廠) Qualifications: 1. 高中(職)以上畢業,不限科系 2. 細心、團隊溝通能力、自我學習能力、邏輯思考能力 3. 基本英文能力(機台介面)、Office 基本操作 4. 無經驗可,有相關經驗者尤佳
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  • 面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 工作經歷不拘 18天前更新
    【本職缺接受台積電官方網站與1111投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4274&source=1111&tags=2024DomesticCampus_1111 Description: R&D Engineers will be part of a grand joint-force working on advanced technologies, including but not limited to exploratory research in advanced device architecture, market-oriented design IP enablement, device and process integration for manufacturability, package-level interconnect solutions, and novel material/equipment/process evaluations. 1. Research & Pathfinding (1) New material and new process pathfinding to enable new device architecture with integration (2) New tool pathfinding for new materials to enable the next nodes (3) Design, execute and analyze experiments to meet R&D engineering specifications (4) Process stability & manufacturability improvement for yield and reliability qualification (5) Process/tool transfer to development R&D or volume manufacturing (Fab) (6) Highly motivated individuals with a strong technical background and teamwork skills 2. Integration (1) Technology definition: design rules, design-technology co-optimization, logic/memory IP evaluations, etc. (2) Technology development infrastructure: productivity enhancement, product inspection methodology, mask-making, and test flow, etc. (3) New test vehicle establishment and validation: improvement of device yield and reliability (learning cycles). Improve yield and reduce defects by quantifying defect attributes using programming skills and developing effective detection methodologies. (4) Customer design enablement: SPICE Modeling and IP qualifications. 3. Module (1) Develop advanced processes, materials, tools, models, and computational methodologies for leading edge technologies. (2) Deliver manufacturable, stable, cost-effective technologies with device performance improvement for yield and reliability qualification. (3) Transfer process and tool to high volume manufacturing fab. 4. R&D Process Center (1) PE: Advanced module process development and baseline sustaining. (2) EE: Handle advanced equipment at R&D stage. Install, warm up, sustain and troubleshooting solve with new technology equipment. (3) MFG: Oversee the daily operations of IC foundry to ensure that all profiling operations, workflow, and customer reports are consistent with agreed upon service operations. Qualifications: 1. Passionate about the development of world-leading technologies. 2. Master‘s degree or above in an engineering or scientific field such as Materials Science Engineering, Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Chemistry or Optics. 3. Solid technical understanding of IC processing equipment, integrated flow, chemistry, and physics. 4. Exhibit good and open communication skills and be able to work within cross-functional teams, including internal and external partners. 5. Fluent in English. 6. Skills in AI and programming are preferred. 7. Strong knowledge of Statistical Process Control (SPC) and/or Design of Experiments (DOE) principles. Having knowledge of machine learning or artificial intelligence is an added advantage. 8. Flexibility in changing priorities and responsibilities to support business needs. 9. Hands-on participation on process or hardware and a strong sense of ownership. 10. Willing to make frequent fab presence. 11. Strong technical problem-solving and analytical skills, based upon fundamental, rather than empirical models is required. 12. Excellent written and spoken communication skills are required.
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  • 面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 工作經歷不拘 18天前更新
    【本職缺接受台積電官方網站與1111投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4275&source=1111&tags=2024DomesticCampus_1111 Description: At the beginning of new module research, IC design engineers and R&D engineers would closely cooperate with customers. Once the new module technologies are developed, we could accomplish the goal of massive production and have customers’ new product launch in a short time. At TSMC, you will have the opportunity to work with the most advanced module technologies, provide solutions to partners in the global IC design ecosystem, and ensure competitiveness in power, performance, and area. 【Physical Designer】 The principal responsibility of the candidate is to perform complete netlist to GDS physical design steps which include floor plan, PNR, timing closure, IR/EM analysis, layout verification, formal verification, and other tape out related tasks. The candidate will work in a talented team to design advanced chips using cutting-edge process nodes while meeting high standard design requirements. 【Standard Cell Engineer】 1. Pathfinding of library characterization for leading edge tech nodes 2. Support industrial standard library kits generation and QC 3. In-house library generation flow and/or utility development 4. RC parasitic extraction analysis and APR related analysis 【Layout Engineer】 1. IC layout for advanced technology (Std. cell/Memory/AMS/IO) 2. Layout structure development for new technology 3. Pathfinding for new technology development 4. Customer engagement and layout support 5. Design and technology co-optimization (DTCO) 6. AI and automation for layout and physical design 【System and Chip Design Solutions Development】 Please refer to the Link: https://careers.tsmc.com/zh_TW/careers/JobDetail?jobId=516 【FE design & DFT】 1. Test chips development for advanced nodes, including physical design (APR), logic synthesis and DFT (Scan insertion + ATPG) 2. Design flow development for test chips design, which requires the programming skills, Tcl, Python, C-shell scripting etc. 3. Technology benchmarking for PPA evaluation of the advanced nodes 4. DTCO (Design & Technology Co-Optimization) pathfinding and development 【SRAM Engineer】 1. SRAM design in advanced nodes for mobile, high-performance computing, IoT, automotive applications. 2. RRAM/MRAM, emerging memory development 3. In memory computing research and development 【Design Flow/Methodology】 1. Advanced technology process design kits (PDK) and tech files (DRC, LVS, RC, etc.) development and technical support 2. Advanced technology design development flow development and technical support 3. Automation program development to support design kits and flow development productivity/quality Qualifications: 1. Master‘s degree in Electrical Engineering or Computer Engineering 2. Strong proficiency in speaking and writing English 3. Thorough understanding of place and route flow 4. Excellent interpersonal and communication skills 5. Self-motivated and possess excellent team spirit
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  • 面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 工作經歷不拘 18天前更新
    【本職缺接受台積電官方網站與1111投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4276&source=1111&tags=2024DomesticCampus_1111 Description: 1. Novel devices developing for specialty technology 2. Device Simulation, Test-chip design tape out and measurement system developing 3. Process flow developing for production 4. Collaborate with related teams for Design Collaterals (DRM/DRC/LVS/SPICE/PDK) developing Qualifications: 1. Master‘s degree or above in an engineering or scientific field such as Materials Science, Engineering, Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Chemistry or Optics. 2. Experienced in process integration or HV/BCD devices developing and characterization. 3. Innovative problem-solving skills 4. Familiar with TCAD simulation is a bonus 5. Process integration & CMOS characterization 6. Solid technical understanding of IC processing equipment, integrated flow, chemistry, and physics. 7. Excellent communication skills and the ability to work within cross-functional teams, including internal and external partners.
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  • 月薪33000~40000元 高雄市大寮區 工作經歷不拘 今天剛更新
    1.長期配合客戶之客情維繫與拜訪 2.新客戶市場開發 3.每月帳款回收追蹤與報告 4.客戶進口電器銷售輔導 5.商品簡易故障排除 6.商品教學使用指導 7.業務獎金依達成另外發放
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    產假產檢假年節獎金員工生日禮金年終獎金
  • 面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 工作經歷不拘 18天前更新
    【本職缺接受台積電官方網站與1111投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4277&source=1111&tags=2024DomesticCampus_1111 Description: As a member of the IIP (Integrated Interconnect & Packaging) team, you will initiate novel package concepts, own and drive advanced package development, new product package structure and configuration optimization. You will be responsible for 3DFabric technology research and development. Including InFO, CoWoS, Coupe and SoIC process/integration development for customer‘s variety applications. Integration: 1. Develop advanced 3DIC (InFO, CoWoS, Coupe and SoIC) process and sustain baseline. 2. Package level reliability, failure mode analysis and improvement plan. 3. Customer technical interface, new tape out and lot handle. 4. Handover developed technologies to manufacturing groups for production. Module Development: 1. Be responsible for CVD / PVD / CMP / Lithography / Etch / Polymer / Bonding / Clean module development for 3DIC projects. 2. New technology, materials survey, and process improvement on 3DIC package structures. 3. Process development and tool transfer to mass-production development. Simulation: 1. Conduct risk assessment and provide mitigation plan for IC packages by simulation and experiment. 2. Practice FEM and DOE in problem solving and path finding particularly on packaging. 3. Continue improvement in simulation methodology, material modeling and script automation. Qualifications: 1. Master‘s degree or above in Chemical Engineering, Material Science, Chemistry, Physics, Mechanical Engineering, or related field in science or engineering 2. Experience in TV design or IC packaging is a plus 3. Good communication skills in Chinese and English 4. Hands-on participation and a strong sense of ownership are required 5. Strong technical problem-solving and analytical skills 6. For simulation positions, mastery of FEM software such as Ansys, LS-DYNA, Abaqus and others
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  • 面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 工作經歷不拘 18天前更新
    【本職缺接受台積電官方網站與1111投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4278&source=1111&tags=2024DomesticCampus_1111 Description: 1. Highly motivated veteran and new talents to join force research and pathfinding in Advanced packaging and system integration technologies for both extending Moore‘s Law and in post-Moore era. 2. Long prospective career path in semiconductor technologies looking at more Moore‘s and beyond Moore‘s Law Eco-industry. Job Description: 1. Integration engineering for process integration and device/system level modeling, including electrical, thermal, and mechanical modeling. 2. Module engineering in advanced FEOL/MEOL/BEOL wafer process modules, and in advanced system packaging, including wafer level fan-out, interposers, and 3D chip stacking 3. Silicon photonics expertise in the following areas: optical components design (lens, modulator, detector, waveguide w/ various materials), photonic circuits design (w/ focus on optical communication), and computer system architect with focus on parallel processing and high-speed networking. Qualifications: 1. Solid skills build-up with hands-on operation. 2. Positions are reserved for those who have strong interest in emerging, exciting and disruptive technologies and for those who enjoys an intellectual-stimulating environment with work-life balance. Engineers and scientists from well-experienced to new in system integration and relevant fields are encouraged to apply. 3. Master’s degree or above in Science/Engineering related field with strong motivation to grow in new field 4. Senior position in system-level pathfinding, innovative heterogeneous system integration, and technology road-mapping 5. Project/team management experience for management position.
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  • 面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 工作經歷不拘 18天前更新
    【本職缺接受台積電官方網站與1111投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://careers.tsmc.com/careers/JobDetail?jobId=4279&source=1111&tags=2024DomesticCampus_1111 Description: 1. A highly motivated individuals with a strong technical background and capabilities to develop and sustain process technologies for logic, flash memory, and specialty products. 2. Working with a team which may include device, integration, yield, lithography, etch and thin films or external suppliers to drive leading-edge integrated module development, control and improvements. 3. Be responsible for sustaining ownership such as day-to-day operations, equipment troubleshooting and mentoring technicians. 我們確保晶片的品質、持續提升良率,提供給客戶具有競爭力且高品質的晶片,讓電子產品不但先進且效能穩定;製程整合工程師為半導體製造中的重要協調者,需要與客戶溝通了解客製化的晶片應用需求,再將訊息帶回廠內,與各工程單位合作。良率精進工程師監控晶片的良率與缺陷,使用量測機台監測晶片的缺陷,找出可能的問題,再與製程解決問題。 Qualifications: 1. Master‘s degree or above in engineering or scientific field such as Materials Science, Engineering, Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Chemistry or Optics. 2. Solid technical understanding of IC processing equipment, integrated flow, chemistry and physics. 3. Exhibit good and open communication skills, be able to work within cross-functional teams, including internal and external partners. 4. Fluent in English. 5. Strong knowledge of Statistical Process Control (SPC) and/or Design of Experiments (DOE) principles. 6. Flexibility in changing priorities and responsibilities to support business needs. 7. Hands-on participation and a strong sense of ownership. 8. Willingness to make frequent fab presence. 在這個領域發光發熱,要具備:半導體元件物理與電性知識、英文與溝通能力、領導與問題解決能力、程式語言作為良率改善工具。
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  • 面議(經常性薪資達4萬元或以上) 新竹縣寶山鄉 工作經歷不拘 18天前更新
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